I. Field of the Invention
The present invention relates generally to a method and apparatus for permanently disabling an integrated circuit (“IC”) input/output (“I/O”) terminal after packaging. More particularly, the present invention relates to placing a disabling device, such as a fuse, between the output driver and the I/O terminal. As a final step in a test process, once all known good I/Os have been determined, the disabling device can be activated to permanently disconnect the I/O terminal from the IC.
II. State of the Art
State of the Art: Before integrated circuits (“IC”) are placed into ordinary operation, they are packaged and tested to determine which I/O terminals function as they were designed to function. The terminals may be in the form of pins, pads, balls or pillars of an array or other conventional configurations. The I/O terminals which do function reliably are called known good I/Os. Based upon the pattern of known good I/Os for a given type of packaged IC, the ICs are sorted, or “binned,” until they are placed onto printed circuit boards for use, often in combination to simulate an entirely functional IC.
The use of unreliable, or known bad, I/Os of an IC produces incorrect or faulty data, or incorrect processing of received data which can cause problems in the operation of a system. To avoid this problem, particularly when fabricating memory modules, a different pattern of printed circuit board trace ends or pads is used for each pattern or combination of known good I/Os. The pattern of trace pads is designed so that no traces contact a known bad I/O. Thus, for each pattern of known good I/Os, design and fabrication of a new printed circuit board trace and trace pad pattern are required. Although this solution of using a variety of printed circuit board designs is effective, it adds cost to the fabrication process and requires excessive printed circuit board inventory. Therefore, it is desirable to avoid the requirement of using different printed circuit board trace patterns for each different pattern of known good I/Os.